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Preliminary
74LCX32652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary)
August 2001 Revised August 2001
74LCX32652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary)
General Description
The LCX32652 contains thirty-two non-inverting bidirectional bus transceivers with 3-STATE outputs providing multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Each byte has separate control inputs which can be shorted together for full 32-bit operation. Output Enable pins (OEABn, OEBAn) are provided to control the transceiver function (see Functional Description). The LCX32652 is designed for low-voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX32652 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs s 2.3V-3.6V VCC specifications provided s 5.7 ns tPD max (VCC = 3.3V), 20 A ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s 24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX32652GX (Note 2) Package Number BGA114A (Preliminary) Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL]
Note 2: BGA package available in Tape and Reel only.
(c) 2001 Fairchild Semiconductor Corporation
DS500634
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Preliminary 74LCX32652 Connection Diagram
Pin Assignment for FBGA
Pin Descriptions
Pin Names 1A0 - 1A15 2A0 - 2A15 1B0 - 1B15 2B0 - 2B15 CPABn, CPBAn SABn, SBAn Clock Pulse Inputs Select Inputs Data Register B Inputs/3-STATE Outputs Description Data Register A Inputs/3-STATE Outputs
OEABn, OEBAn Output Enable Inputs NC No Connect
FBGA Pin Assignments
1 A B C D E F G (Top Thru View) H J K L M N P R T U V W 1A0 1A2 1A4 1A6 1A8 1A10 1A12 1A13 1A15 NC 2A0 2A2 2A4 2A6 2A8 2A10 2A12 2A13 2A15 2 SAB1 1A1 1A3 1A5 1A7 1A9 1A11 1A14 SAB2 3 4 5 SBA1 1B1 1B3 1B5 1B7 1B9 1B11 1B14 SBA2 6 1B0 1B2 1B4 1B6 1B8 1B10 1B12 1B13 1B15 NC 2B0 2B2 2B4 2B6 2B8 2B10 2B12 2B13 2B15 CPAB1 CPBA1 OEAB1 OEBA1 GND VCC GND GND VCC GND GND VCC GND GND VCC GND
CPAB2 CPBA2
CPAB3 OEAB2 OEBA2 CPBA3 SAB3 2A1 2A3 2A5 2A7 2A9 2A11 2A14 SAB4 OEAB3 OEBA3 GND VCC GND GND VCC GND GND VCC GND GND VCC GND SBA3 2B1 2B3 2B5 2B7 2B9 2B11 2B14 SBA4
CPAB4 CPBA4 OEAB4 OEBA4
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Preliminary
74LCX32652
Truth Table
(Note 3) Inputs OEAB1 OEBA1 CPAB1 CPBA1 L L X H L L L L H H H H H H H X L L L H H L H or L SAB1 X X X X X X X X L H H SBA1 X X X X X X L H X X H Output Output Input Output Input Input Not Specified Output Output Not Specified Output Input Input Input Inputs/Outputs (Note 4) 1A0 thru 1A7 Input 1B0 thru 1B7 Input Operating Mode Isolation Store A and B Data Store A, Hold B Store A in Both Registers Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
H or L X X X H or L H or L

H or L H or L

X X X
H or L
H or L
Note 3: Data I/O paths (1A and 1B: 0 - 7) is shown. This also applies to data I/O (1A and 1B: 8 - 15) and #2 control pins, to data (2A and 2B: 0 - 7) and #3 control pins, to data (2A and 2B: 8 - 15) and #4 control pins. Note 4: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
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Preliminary 74LCX32652 Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the 74LCX32652 for data register I/O 1A and 1B: 0 - 7. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.
Real-Time Transfer Bus B to Bus A
Real-Time Transfer Bus A to Bus B
OEAB1 OEBA1 CPAB1 CPBA1 L L X X
SAB1 X
SBA1 L
OEAB1 OEBA1 CPAB1 CPBA1 H H X Storage X
SAB1 L
SBA1 X
Transfer Storage Data to A or B
OEAB1 OEBA1 CPAB1 CPBA1 H L H or L H or L
SAB1 H
SBA1 H
OEAB1 OEBA1 CPAB1 CPBA1 X L L H X H X

SAB1 X X X
SBA1 X X X

X
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Preliminary
74LCX32652
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Preliminary 74LCX32652 Logic Diagrams
(Continued)
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Preliminary
74LCX32652
Absolute Maximum Ratings(Note 5)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 6) VI < GND VO < GND VO > VCC V mA mA mA mA mA
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -50 -50 +50 50 100 100 -65 to +150
C
Recommended Operating Conditions (Note 7)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V VCC = 2.3V - 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V
24 12 8 -40
0 85 10 mA
C
ns/V
t/V
Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Note 7: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -8 mA IOH = -12 mA IOH = -18 mA IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF Input Leakage Current 3-STATE I/O Leakage Power-Off Leakage Current 0 VI 5.5V 0 VO 5.5V VI = V IH or VIL VI or VO = 5.5V Conditions VCC (V) 2.3 - 2.7 2.7 - 3.6 2.3 - 2.7 2.7 - 3.6 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 - 3.6 0 VCC - 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 5.0 5.0 10 A A A V V TA = -40C to +85C Min 1.7 2.0 0.7 0.8 Max Units V V
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Preliminary 74LCX32652 DC Electrical Characteristics
Symbol ICC ICC Parameter Quiescent Supply Current Increase in ICC per Input
(Continued)
VCC (V) 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6 TA = -40C to +85C Min Max 20 20 500 A A
Conditions VI = VCC or GND 3.6V VI, VO 5.5V (Note 8) VIH = VCC -0.6V
Units
Note 8: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter VCC = 3.3V 0.3V CL = 50 pF Min fMAX tPHL tPLH tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW Setup Time Hold Time Pulse Width Output Disable Time Maximum Clock Frequency Propagation Delay Bus to Bus Propagation Delay Clock to Bus Propagation Delay Select to Bus Output Enable Time 170 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 5.7 5.7 6.2 6.2 6.5 6.5 7.0 7.0 6.5 6.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 6.2 6.2 7.0 7.0 7.0 7.0 8.0 8.0 7.0 7.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 2.0 3.5 6.8 6.8 7.4 7.4 7.8 7.8 9.1 9.1 7.8 7.8 Max VCC = 2.7V CL = 50 pF Min Max VCC = 2.5V 0.2V CL = 30 pF Min Max MHz ns ns ns ns ns ns ns ns Units
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL =0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL =0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25C Typical 0.8 0.6 -0.8 -0.6 V V Units
Capacitance
Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF
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Preliminary
74LCX32652
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Switch Open 6V at VCC = 3.3 0.3V, and 2.7V VCC x 2 at VCC = 2.5 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1 MHz, tr = tf = 3 ns) Symbol Vmi Vmo Vx Vy VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V
trise and tfall
2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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Preliminary 74LCX32652 Schematic Diagram Generic for LCX Family
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Preliminary
74LCX32652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary)
Physical Dimensions inches (millimeters) unless otherwise noted
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Preliminary
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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